1. Field of the Invention
This invention relates to a semiconductor device and, in particular, relates to a DLL (Delay Locked Loop) circuit using a result of ZQ calibration adapted for adjusting the impedance of an output circuit and to a semiconductor device incorporating such a DLL circuit.
2. Description of the Related Art
Recent electronic systems have been speeded up in operation, wherein the data transfer rate between semiconductor devices forming the system has been highly increased. Further, also in each of the semiconductor devices, high-speed data transfer operation is required. Accordingly, a clock synchronization system synchronous with a clock signal (hereinafter also referred to simply as a “clock”) is employed inside the semiconductor device. For example, there is a synchronous dynamic random access memory (hereinafter abbreviated as a “SDRAM”) as a semiconductor memory device. Further, a DDR (Double Data Rate)-SDRAM, a DDR2-SDRAM, and a DDR3-SDRAM each synchronous with the leading and trailing edges of a clock have been developed as advanced SDRAMs.
For synchronization with an external clock, these advanced SDRAMs each employ a DLL circuit to thereby synchronize the timing between an internal clock and the external clock. FIG. 1A is a block diagram of a conventional DLL circuit. Since a DQ buffer used in the DLL circuit has a terminating element on the outside thereof, the amplitude of DQ buffer output is suppressed to a small value as shown in FIG. 1B. On the other hand, since a DQ replica has no terminating element, a DQ replica output (RCLK) exhibits its full amplitude as shown in FIG. 1C.
Inclinations and delay amounts (tPD) of these outputs change due to variations in temperature, voltage, and process, and delay times Δt1 and Δt2 of these outputs differ from each other due to a difference in amplitude therebetween. A delay line of the DLL circuit operates so as to synchronize the output of the DQ replica with an external clock CK. Therefore, as shown in FIG. 2, a difference between Δt1 and Δt2 is, as it is, observed as a skew between the output of the DQ buffer and the external clock.
In the conventional SDRAM, there is no function of measuring changes in delay amount caused by variations in temperature, voltage, and threshold voltage (Vth) of MOS transistors and feeding them back. Therefore, it is difficult to perform control that can absorb those variations. That is, there has been a problem that variations in delay amount of the DQ buffer system and delay amount of the DQ replica system caused by variations in temperature, voltage, and Vth of MOS transistors become skews as they are and thus the DLL circuit cannot achieve high-speed operation.
With respect to such a DLL circuit, there is Prior Document 1 (Japanese Unexamined Patent Application Publication (JP-A) No. Hei 11-086545). With respect to a calibration circuit for adjusting the impedance of an output circuit, there is Prior Document 2 (Japanese Unexamined Patent Application Publication (JP-A) No. 2004-032070) or Prior Document 3 (Japanese Unexamined Patent Application Publication (JP-A) No. 2004-145709). Further, with respect to a memory system, there is Prior Document 4 (Japanese Unexamined Patent Application Publication (JP-A) No. 2001-159999).
Prior Document 1 discloses a DLL circuit that detects a phase difference between an output circuit system and a dummy output circuit system to thereby eliminate a phase difference between clocks. Prior Document 2 discloses a calibration circuit that comprises fine-adjustment buffers connected in parallel, compares between a potential at a connection point and a reference potential, operates a counter in response to a comparison result, and adjusts the impedance of an output circuit according to a signal from the counter.
Prior Document 3 discloses a calibration circuit that adjusts the impedance of an output circuit according to a control signal from the exterior. Prior Document 4 discloses a memory system in which the lengths of data transmission lines are measured by monitoring reflected waves obtained when corresponding memory chips output data onto the data transmission lines, respectively, and, based on the measurement results, a system controller determines a setup time and a hold time per memory chip.
However, in the conventional DLL circuit, there is no function of measuring variations in temperature, voltage, and Vth of MOS transistors and feeding them back. Therefore, there remains the problem that variations in delay amount of the output system and delay amount of the replica system caused by variations in temperature, voltage, and Vth of MOS transistors become skews as they are and thus the high-speed operation cannot be achieved. Further, also in the conventional calibration circuits and memory system, no improvement scheme for these skews is proposed and thus there still remains the problem.
As described above, in the DLL circuit, there is no function of measuring variations in temperature, voltage, and Vth of MOS transistors and feeding them back. Therefore, there is the problem that variations in delay amount of the DQ buffer system path and delay amount of the DQ replica system path caused by variations in temperature, voltage, and Vth of MOS transistors become skews as they are and thus the high-speed operation cannot be achieved.